Bachelor's degree in Computer Science, Electrical Engineering, or related field., 5+ years of hands-on experience in Synthesis and Static Timing Analysis., Proficiency in TCL scripting and UNIX environment., Strong knowledge of timing closure at subsystem, block, and chip levels..
Key responsibilities:
Lead and mentor a team of 4 to 5 members in STA and Synthesis processes.
Coordinate with design team counterparts in RTL design, Physical design, and DFT.
Perform logical equivalence checks and fix timing violations using manual ECOs.
Engage in client interface and ensure effective communication with stakeholders.
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