Offer summary

Qualifications:

MSc or PhD in Electrical or Computer Engineering., Experience in Matlab/Simulink/C modeling of circuits and systems., Background in digital signal processing and high-speed analog CMOS circuit design., Familiarity with high-speed serial data protocols and link budget analysis..

Key responsabilities:

Define architecture and specifications for transmitter and receiver designs.

Design and maintain system level models for performance analysis.

Analyze signal and power integrity requirements for high-speed links.

Assist customers with system level performance and algorithmic issues.

Job description

System Level Architect

You will be part of an R&D team developing >100Gbps NRZ and PAM4 serial-link transceivers as part of our Enterprise Serdes team for PCIe and Ethernet protocols. We are looking for an engineer with theoretical knowledge and practical experience to contribute and to lead the team. You will work with a cross functional design team of analog and digital designers, and hardware engineers.

You will be involved in all stages of development including:

Architecture: definition of architecture and specifications for the transmitter and receiver
Modelling: design and maintenance of the system level model
Signal/Power Integrity: analyzing different signal and power integrity requirements
Sign-off: system level simulation of the design performance across multiple protocols and channels
Silicon: qualification and correlation of performance and algorithms in silicon
Customers: assisting customers on system level performance and algorithmic issues

You have a MSc or PhD in Electrical or Computer Engineering.

Due to the cross disciplinary nature of this position, key qualifications include one or more of the following…

Modelling - experience in Matlab/Simulink/C modeling of circuits and systems
Communications theory – equalization, coding, noise/crosstalk filtering
Digital – background in digital signal process (DSP)
Analog – background in high-speed analog CMOS circuit design
Hardware – awareness on per-protocol handing of RX and TX adaptation ; hands on experience in measurement of transceiver performance

Experience:

Familiarity with modelling of SERDES transmitters and receivers in Matlab or similar tool
Knowledge of circuit topologies in high-speed Rx/Tx SerDes PHY
Understanding of Tx/Rx equalization techniques.
Knowledge of CDR architectures and CDR loop dynamics
Experience in analyzing link budgets for either NRZ and PAM4 high-speed serial links
Knowledge about common high-speed serial data protocols including Ethernet, OIF, JESD, CPRI
Experience in lab testing of high-speed serial links

Required profile