Transceiver Integration Architect

Job Details:

Job Description:

We are seeking a highly skilled and experienced Transceiver (XCVR) Integration Architect to lead the definition and architecture of transceiver subsystems for Altera’s FPGA portfolio. This individual will drive the selection and integration of SerDes (Serializer/Deserializer) and Layer 2+ IP stacks (e.g., Ethernet, PCIe) to support scalable FPGA solutions across low, mid, and high-performance products.

Key Responsibilities

• Architect transceiver subsystems for Altera FPGAs, including selection and integration of SerDes and Layer 2+ protocols such as Ethernet and PCIe.

• Define SerDes requirements in collaboration with the SerDes team; co-architect end-to-end solutions that balance protocol support, integration complexity, and usability for FPGA applications.

• Serve as the technical interface between the SerDes team and broader design, integration, and system engineering teams.

• Define integration requirements for building complete subsystems with IP, bridges, reset logic, and power plans optimized for usability, performance, and power efficiency.

• Partner with soft IP and software teams to ensure seamless integration and a smooth user experience for end customers.

• Monitor and analyze industry trends, customer requirements, and evolving standards to guide product direction and architecture strategies.

• Provide technical leadership across cross-functional teams including validation, verification, packaging, software, planning, and product marketing.

• Represent Altera in customer and industry engagements, helping to shape future FPGA capabilities based on market feedback.

Qualifications:

Minimum Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

• 10+ years of experience in FPGA or ASIC architecture/design with a focus on high-speed transceivers and protocol IP integration.

Preferred Qualifications:

• Deep understanding of SerDes technology, protocols (Ethernet, PCIe, CXL, etc.), and transceiver subsystem architecture.

• Experience defining and integrating soft and hard IP within FPGA environments.

• Knowledge of power management strategies, IP interface design, reset architecture, and software interaction models.

• Proven track record of technical leadership and cross-functional collaboration.

• Strong communication skills and ability to influence product direction at a senior level.

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