Offer summary

Qualifications:

BSc or MSc in Electrical Engineering or Computer Science., At least 8 years of experience in VLSI backend (RTL to GDS)., Minimum of 5 years experience in Static Timing Analysis (STA) using Prime-Time or similar tools., Strong knowledge of full chip STA, timing closure, and signoff methodologies..

Key responsibilities:

Participate in STA activities for blocks, subsystems, and full chips from definition to tape-out.

Analyze timing results, verify correctness, and manage timing budgets across partitions.

Own and manage timing constraints for STA and place-and-route flows.

Collaborate with architecture, design, PD, and DFT teams to ensure timing closure and product success.

Job description

Description

NextSilicon is redefining high-performance computing. Our accelerated compute solutions use intelligent, adaptive algorithms to significantly boost the performance of supercomputers, driving the industry into a new era.

Our unique software-defined hardware architecture enables HPC to deliver on its promise of breakthroughs across advanced research fields — from climate science to artificial intelligence.

At NextSilicon, our work is guided by three core values:

Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

We are looking for an experienced STA Engineer to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs.

Requirements

BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years experience in STA (Prime-Time/Signoff).
Experience Full chip STA on complex SoCs experience.
Expert knowledge and hands-on experience in timing closure & signoff methodologies.
Good knowledge of DFT architecture and DFT timing related issues
Good knowledge of Async timing concepts & verification.
Good knowledge of the full backend flows from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs)

Responsibilities

Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO
Analyze timing results, verify correctness and provide timing budget for the different partitions.
Own the timing constraints both for STA and P&R flow.
Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success
Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages.
Participating in design methodology, reviews and tool automation work and definition
As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets

Required profile