FPGA IP Software Development Engineer

Job Details:

Job Description:

Join Altera IP solutions team and work on cutting edge FPGA RTL and IP design!  Altera's IP Solutions Engineering (IPSE) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Altera’s FPGA devices. These solutions are provided as highly configurable intellectual property (IP) cores that are fully integrated with Altera's software CAD tool, Quartus Prime. The IP Cores we develop include high-speed interface IPs such as PHY-lite, MIPI, and LVDS, which are designed for high-speed data transmission and used in applications like video processing, display interfaces, chip-to-chip communication, and chip testing. Altera's IP cores provide configurable access to the high-speed, high-bandwidth, low-latency interfaces, leveraging dedicated and specialized silicon subsystems in the FPGA. The constantly rising speed and complexity of video, display, and high-speed data transmission interfaces presents a challenging design problem that requires system-level knowledge of silicon, software, IP, and customer applications.

As an IP Design Engineer, you will work with a team of engineers to develop and verify state-of-the-art PHY-lite, MIPI, and LVDS-based IP cores for high-speed data transmission. You will be working on advanced FPGA architectures, design definition, implementation, and verification. Additionally, you will also be developing design examples and simulation models, accompanied by a rich set of technical documentation. In this role, you will work closely with multiple teams, including silicon design and validation, post-silicon validation, application engineering, and customer experience teams, to ensure seamless development, integration, and optimization of high-speed interface IP solutions.

Your specific responsibilities will include, but are not limited to the following:

• Architecture and Design based on the latest protocol specifications for video processing, display interfaces, chip-to-chip, and high-speed data transmission interfaces

• RTL development

• Device support and CAD tool integration

• Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)

• Hardware power-on and debug

• New product release and rollout support

• Customer technical support

Salary Range

Our compensation reflects the cost of labor within the US market. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$115.1k - $166.7k USD

Qualifications:

The candidate should possess the following behavioral traits:

• Strong skills in communication, initiative, innovation, and teamwork

• Highly motivated to learn and adapt to fast-changing technologies and environments

• Excellent problem-solving skills and attention to detail

• Demonstrate fundamental values such as accountability, integrity, and a winning mindset

• Collaborative mindset, strong influencing skills, and a willingness to work across geographical locations

Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• BS degree with 4+ years of experience or MS degree with 3+ years of experience or PhD degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or related field with experience in:

• Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification

• Scripting languages and/or software programming (e.g. Python/TCL/Perl and/or C/C++)

Preferred Qualifications:

• 6+ year of experience with IP Integration, RTL Design, SystemVerilog, Verilog and/or VHDL

• Experience with scripting languages and/or software programming (e.g. Python/TCL/Perl and/or C/C++)

• FPGA design experience

• Experience with RTL simulation, timing closure, Static Timing Analysis

• Experience with high speed SerDes IOs and physical layer design for chip-to-chip interconnect systems

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