Offer summary
Qualifications:
Bachelor’s or Master’s in Electrical or Computer Science, 4 years of Design Verification experience, Proficient in SystemVerilog and UVM, Experience with verification tools and methodologies, Knowledge of standard protocols like PCIe and DDR4/5.
Key responsabilities:
- Review product designs for failure points
- Design verification methodology and testing environments
- Plan sequence for testing operations and protocols
- Write final test procedures and train QC staff
- Conduct debugging and work in FPGA emulated platforms